COMP_LP0_IN_M_SEL=Val_0x0, COMP_LP0_IN_P_SEL=Val_0x0, COMP_LP0_HYST=Val_0x0, OSC_76M_DIV_CTRL_ACTIVE=Val_0x0, PMUBG_VREF_CONT=Val_0b0000, OSC_76M_DIV_CTRL_STBY=Val_0x0, DIG_LDO_CONT=Val_0b0000
VBAT Analog Control Register 2
| PMUBG_VREF_CONT | Calibration for PMU bandgap: Step: 1% 0 (Val_0b0000): -7% 15 (Val_0b1111): +8% |
| DIG_LDO_18_EN | Enables 1.8-V digital LDO (LDO-4). Used for MRAM and EFUSE. |
| DIG_LDO_CONT | LDO-4 output voltage control: Step: 20 mV 0 (Val_0b0000): 1.58 V 15 (Val_0b1111): 1.88 V |
| OSC_76MRC_CTRL_0 | Control for 76-MHz RC oscillator frequency, LSB. Used with OSC_76MRC_CTRL_51 |
| OSC_76M_DIV_CTRL_ACTIVE | 76-MHz oscillator divider control in GO, READY, and IDLE modes. 0 (Val_0x0): 76.8 MHz 1 (Val_0x1): 38.4 MHz 2 (Val_0x2): 19.2 MHz 3 (Val_0x3): 9.6 MHz 4 (Val_0x4): 4.8 MHz 5 (Val_0x5): 2.4 MHz 6 (Val_0x6): 1.2 MHz 7 (Val_0x7): 600 kHz |
| OSC_76MRC_CTRL_51 | Control for 76-MHz RC oscillator frequency. Bits [5-1]. Used with OSC_76MRC_CTRL_0 (bit 0). Step: 1.3% 000000: -10% 111111: +10% |
| OSC_76M_DIV_CTRL_STBY | 76-MHz oscillator divider control in STANDBY mode. 0 (Val_0x0): 76.8 MHz 1 (Val_0x1): 38.4 MHz 2 (Val_0x2): 19.2 MHz 3 (Val_0x3): 4.8 MHz 4 (Val_0x4): 1.2 MHz 5 (Val_0x5): 600 kHz 6 (Val_0x6): 300 kHz 7 (Val_0x7): 75 kHz |
| ANA_PERIPH_BG_ENA | Enable precision bandgap for analog peripherals. |
| ANA_PERIPH_LDO_EN | Enable Analog Peripherals LDO (LDO-5) |
| COMP_LP_EN | Enables LPCMP |
| COMP_LP0_IN_P_SEL | Selects input to positive terminal of LPCMP: 0 (Val_0x0): LPCMP_IN0 pin 1 (Val_0x1): LPCMP_IN1 pin 2 (Val_0x2): LPCMP_IN2 pin 3 (Val_0x3): LPCMP_IN3 pin |
| COMP_LP0_IN_M_SEL | Selects input to negative terminal of LPCMP: 0 (Val_0x0): Internal AON Vref (0.8 V) 1 (Val_0x1): VREF_IN0 pin 2 (Val_0x2): VREF_IN1 pin 3 (Val_0x3): VREF_IN2 pin |
| COMP_LP0_HYST | Sets LPCMP hysteresis level. 6-mV steps 0 (Val_0x0): 0 mV 7 (Val_0x7): 45 mV |